Adaptive physical reasoning for chiplets and advanced packaging. Resolution on demand puts full fidelity where a design can fail and speed everywhere else, from fast analysis and design exploration to verified sign-off.
Processor core at layout level: the modeled structure (inset) and the signal wires of M1–M4 over the device layer at 50 nm, each coloured by its own temperature rise. Actual modeled layout and thermal results; heights stretched.
Running physics everywhere, all the time, at one resolution still spends most of the compute on regions that cannot fail. Adaptive physical reasoning puts fidelity where the physics is hard, at the resolution you ask for, so one analysis is both high fidelity and computationally efficient.
The whole package stays in the model. Fine resolution goes where you need it: hot spots, die corners, the gaps between dies. Everything else stays coarse.
Full package (left) and its hottest compute die at 20 µm (right, own colour scale). Modeled package, synthetic power maps.
AI surrogates explore, reduced-order solvers refine, and the full numerical reference signs off. Each question uses the cheapest model that is still right.
Fidelity and compute stop being a trade-off made once per project. They are decided on demand: per region, per candidate, per question.
Uniform grids fine enough to see these features need terabytes of memory. Three new white papers show the same resolution on full accelerator packages, on a single machine. All white papers →
Modeled accelerator packages with synthetic layouts or power maps, not vendor data. Uniform-grid figures are estimates and projections, not solved runs. Results will differ on other hardware.
Advanced packages fail where physics couples, and margins are only as good as the reference behind them.
IR-drop heats the die, heat ages the wires, mismatch bends the package. Thermal, warpage, electromigration and power-integrity engines work together, so real temperature maps drive reliability instead of a uniform-die guess.
Each engine carries its own full numerical reference. Fast answers are confirmed against it in the same tool, and the accuracy is published in our white papers and benchmarks.
Start from the files your teams already have: 3Dblox, GDSII, IPC-2581 and ODB++ in, structured results out. Works with OpenROAD, commercial EDA flows and agentic platforms such as Ergodex AI.
Every engine pairs fast AI and reduced-order models with a full numerical reference, and every analysis is a CLI call an agent can make. Our main focus today is thermal and warpage: ThermStack and WarpStack.
Temperature fields from chip, package and board design files, with hot spots resolved on demand, from 20 µm on a package to 50 nm on a die.
Package warpage and corner stress in one run, from fast design sweeps to sign-off.
Electromigration, thermomigration and IR-drop solved together, with lifetime prediction.
Transient power-grid simulation and dynamic IR-drop on full-chip grids.
Set the objectives once. Agents propose candidates, our engines evaluate each at the resolution it needs, and a separate verifier signs off on the numerical reference.
See it on your own 2.5D/3D chiplet design, or read the technical white papers first.
