Tools — Hybrid Numerical + AI Engines

Thermal analysis

ThermStack

FEM-grade static and transient thermal analysis for 2.5D and 3D chiplet stacks — up to 1400× faster than 3D FEM.

Vertical stacking traps heat between layers, and accelerators now push 700–1200 W — so peak junction temperature decides whether a design ships. ThermStack breaks the in-plane temperature field into independent spectral (cosine) modes, resolves each one down through the physical layer stack, and reassembles the full 3D map. One giant coupled 3D problem becomes hundreds of tiny independent ones, solved all at once.

Resolved 3D heat maps — full-chip, full-stack temperature fields for 2.5D and 3D assemblies, every die, layer and interposer resolved through-thickness.
Transient response — drive the model with arbitrary power waveforms and get the full temperature history at every node.
Real-time fast — ~0.02 s per steady-state solve; transients well under a second. Fast enough for ~50 Hz runtime thermal management.
Two solver modes — ThermStack (thickness-resolved, most accurate) and ThermStack-2D (layer-averaged, fastest) span the speed/accuracy tradeoff on identical inputs.
Real chiplet stacks — validated to 11 layers: 2.5D interposers, 3D logic stacks, HBM, CPU and RF packages, with anisotropic materials, interface resistance and convective cooling.
Batched & scriptable — modes solve independently, so workloads batch naturally across multi-core CPUs and GPUs.

Method	Avg RMSE vs FEM-3D	Runtime / case	Note
FEM-3D reference	—	12.7 s	ground truth
SOV baseline	0.225 K	0.047 s	semi-analytical
GIT baseline	0.219 K	0.348 s	semi-analytical
ThermStack-2D	0.444 K	0.016 s	fastest
ThermStack	0.214 K	0.020 s	most accurate

Averaged over 18 static cases (6 real designs × 3 power inputs, up to 11 layers) against a consistent-mass 3D-FEM reference. Transient: 12 cases × 100 time steps, 1.22 K RMSE at a mean 1036× speedup. Peak static speedup 1410× (2.5D chiplet).

At a glance

Peak speedup vs 3D FEM1410×

Mean static RMSE0.21 K

Steady-state solve0.02 s

Transient mean speedup1036×

Stack depth validated11 layers

Cases benchmarked30

AI engines · ThermStack-AI

Two neural solvers developed beside the two numerical ones. The PINN covers parametric design-space sweeps and uncertainty quantification; the transformer returns live thermal maps straight from on-chip telemetry.

AI inference0.59 ms

Mean error0.23 K

Solver engines2 num + 2 AI

spectral solver static + transient 2.5D / 3D stacks anisotropic materials GPU-ready ThermStack-AI agentic CLI

Validated against

Measured power maps from Qualcomm Snapdragon, Google Coral Edge-TPU, Intel Core i5/i7, plus HBM3 stacks, 5 nm CPUs, GaAs RF PAs and an 11-layer 3D IC — all against a full 3D-FEM reference that ships alongside.

Thermal-mechanical stress

WarpStack

Thermal warpage analysis for 2.5D and 3D chiplet packages — fast 2D screening plus detailed 3D sign-off, from one design description.

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Stacking silicon, interposers and memory bonds materials with very different expansion rates. As the assembly cools from bonding to operating temperature, those mismatches bow the package — and a few microns decides whether solder bumps pull apart into opens or merge into shorts. WarpStack predicts that bow, and where it peaks, in design rather than on the assembly line.

2D screening in a blink — a full warpage map in ~0.35 s, the same speed whether the design has 3 layers or 11. Sweep hundreds of floorplans without waiting.
3D for the hard cases — a layer-wise 3D FEM resolves the package through its full thickness, reporting the die-level active surface and the package surface separately.
Real multi-layer stacks — arbitrary stacks of substrates, interposers, bumps, dies, spreaders and lids, with per-layer materials and per-die placement. Validated 3–11 layers, 10–18 dies.
Clear visual output — warpage heatmaps, cross-sections, a 3D stack view, plus peak-to-peak bow in microns.
2D vs 3D compare mode — run both and see exactly where they agree, so you know which designs the fast path can screen and which truly need 3D.
Scriptable — CLI with structured JSON in, CSV/JSON out; one design or a whole batch.

Design	Layers	Dies	2D solve	2D bow	3D bow	2D speedup
11-layer 3D chiplet	11	16	0.356 s	—	—	1411×
2.5D chiplet	9	14	0.347 s	50 µm	44 µm	285×
5 nm CPU	7	18	0.347 s	—	—	153×
HBM3 memory stack	6	10	0.346 s	10.1 µm	8.3 µm	33×
Arbitrary-layer module	5	12	0.345 s	251 µm	269 µm	—
Planar 16-die array	3	16	0.347 s	1465 µm	1256 µm	26×

Nine 2.5D/3D benchmark designs, each solved with both methods. 3D solve time ranges from ~9 s to ~8 minutes; the 2D solve stays near 0.35 s regardless of layer count, die count, or package size (5 mm to 200 mm on a side). On most designs, 2D lands within roughly 10–20% of the 3D peak warpage.

At a glance

2D warpage solve~0.35 s

2D vs 3D speedupup to 1411×

Layers in 3Dup to 11

Dies per design10 – 18

2D vs 3D agreement81 – 93%

Benchmarks9 designs

AI engine · WarpStack-AI

A graph network developed to follow the package's own layer and interconnect topology, returning numerical-grade warpage maps in milliseconds — fast enough to run inside the optimization loop itself.

AI inference~1.5 ms

vs. 3D numerical120,000×

Error vs ground truth~1%

2D laminate FEM 3D layer-wise FEM peak-to-peak bow solder open / short risk compare mode WarpStack-AI agentic CLI

Why microns matter

Convex (∩) bow pulls edge bumps apart into opens; concave (∪) bow presses center bumps into shorts. Too much bow also cracks dies, delaminates layers, and drops assembly yield.

At the frontier

Industry analysis attributed NVIDIA's Blackwell delay to CTE mismatch between the GPU chiplets, LSI bridges, RDL interposer and substrate in TSMC's CoWoS-L package — warpage severe enough to force a redesign of the top metal layers and bump structures. This is the failure mode WarpStack computes, at a speed that lets it run while the stack-up is still a choice.

Phil Garrou, Packaging IFTLE 607 — 3D InCites, Oct 2024 ↗

Electromigration & reliability

MetalStack

Full-chip, temperature-aware multiphysics: coupled electromigration, thermomigration and IR-drop over real power-grid networks.

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Black's equation and Blech's limit are over-conservative; even physics-based Korhonen solvers usually assume a uniform die temperature. MetalStack closes that gap. It solves the discretized Korhonen stress equation coupled to an MNA IR-drop solver, driven by real spatial thermal maps — and the results show that where the hotspot sits relative to the critical current paths can matter more than the average temperature.

Coupled EM / TM / IR-drop — electromigration and thermomigration evolve together with the electrical network, not in isolation.
Realistic spatial thermal maps — accepts external chip-level temperature fields, including real measured profiles, in place of a uniform-die assumption.
Joule self-heating — per-node, per-segment wire temperature from current density and path resistance, superimposed on the ambient field.
Iterative resistance feedback — void-driven resistance changes are written back to the netlist, so every IR-drop solve reflects the grid's current aging state.
Monte Carlo lifetime prediction — TTF distributions, not a single number, across sampled material parameters.
Flow integration — operates on power grids from open-source OpenROAD and major commercial EDA flows, retaining via resistances for early-failure assessment.

Design	Trees	Max nodes	Init IR %	Final IR %	TTF (s)	Krylov speedup
armcore_logic	208	10,900	8.85	22.21	1.05×10⁷	1.29×
risc_core	186	5,750	6.19	29.64	2.47×10⁷	1.21×
JPEG_new	178	6,300	6.56	6.77	>5.0×10⁷	1.26×
AES_new	97	3,450	6.14	6.86	>5.0×10⁷	1.21×
armcore_pad	68	1,700	0.29	0.29	>5.0×10⁷	1.18×
dual_ram	55	1,450	0.09	0.10	>5.0×10⁷	1.50×

Power grids extracted from a major commercial EDA design flow, synthesized and placed-and-routed with the SAED32 (32/28 nm) library. Rational Krylov acceleration achieves 0% error on TTF and final-IR metrics vs. the full FDTD reference.

At a glance

Physics coupledEM + TM + IR

Designs validated6 industrial

Largest tree resolved10,900 nodes

Krylov metric error0%

Monte Carlo samples100 / design

Flows supportedOpenROAD · commercial

AI engine · MetalStack-AI

A physics-informed neural engine developed beside MetalStack Core. Explore fast with AI, confirm against the numerical engine — every answer carries its own confidence range, with no separate statistical run to set up.

vs. numerical engineup to 86×

vs. commercial toolsup to 243×

Of referencewithin 0.05%

Korhonen stress thermomigration Joule self-heating Monte Carlo TTF via-aware early failure MetalStack-AI agentic CLI

Why spatial thermal wins

On the RISC-V core, two 353 K thermal maps with nearly identical peak temperature (387.1 K vs 387.6 K) give opposite verdicts — one fails at ~9.4 months, the other never crosses the threshold. Average temperature alone is not sufficient for sign-off.

Power integrity

GridStack

Rapid Analysis of Power-grid Transients via Order Reduction — full transient P/G simulation and dynamic IR-drop on million-node grids.

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Dynamic IR-drop is decided by the full time-domain response of a mesh with millions of nodes, thousands of switching sources, and thousands of time steps. A direct solver re-solves that system step after step — trustworthy, far too slow to keep in a design loop. GridStack never re-solves the full mesh: it distills the grid's dominant dynamics into a compact order-10 rational-Krylov model, marches that through time, and projects back onto your probe nodes.

Full time-domain waveforms — V(t) at every probe node under arbitrary switching-current profiles; droop, settling, and dynamic IR-drop step by step.
Advanced Krylov subspace reduction — a rational subspace places expansion points for the transient window; an order-10 model reproduces the full response.
Domain decomposition — partitions the grid into balanced subdomains solved in parallel across multi-core CPUs and GPUs, then stitched at shared boundary nodes.
Full-chip visualization — metal-layer structure, rail-aware 2D IR-drop / VSS-bounce maps, and 3D drop surfaces.
Built for sweeps — once the reduced model is built, re-running new current scenarios, decap placements, or floorplans is cheap.

Circuit	Nodes	Direct CPU	GridStack CPU	Speedup	Max norm. err
ibmpg1t	54,265	2.27 s	0.41 s	5.57×	5.62e-06
ibmpg2t	164,897	14.10 s	1.19 s	11.86×	7.39e-08
ibmpg3t	1,043,444	203.93 s	32.64 s	6.25×	7.94e-07

Reference: direct back-Euler transient solve on the IBM power-grid benchmarks, 1,001 time points, 20 golden probe nodes per circuit, reduction order 10. Average speedup 7.9×.

Four hybrid engines: numerical physics and AI in one tool

ThermStack

WarpStack

MetalStack

GridStack

One suite, the whole integrity picture.