Product suite

Four hybrid engines: numerical physics and AI in one tool

Power integrity, electromigration, thermal, and thermal-mechanical stress — each validated against a ground-truth reference solver, each callable from an autonomous design agent. Three of the four have an AI engine developed beside the numerical one, sharing the same inputs, CLI and output schema: explore at millisecond speed, then confirm against ground truth without leaving the tool.

Coupled effects → callable engines

Each coupling the industry now calls first-order maps onto an engine fast enough for an agent to invoke thousands of times.

Thermal–mechanical — CTE mismatch concentrates stress on microbumps, solder joints and TSVs across the stack
→
WarpStack Warpage and peak-to-peak bow, MOR sweep to 3D sign-off
Electrical–thermal — power density raises temperature, which raises resistance and IR-drop, shifts mobility and leakage
→
GridStack + ThermStack Transient IR-drop coupled to full temperature fields
Thermal-driven reliability — Joule self-heating accelerates electromigration and thermomigration in the power grid
→
MetalStack EM + TM + IR solved together, with Monte Carlo lifetime
Power delivery noise — simultaneous switching couples into timing across die, package and board
→
GridStack Full transient power-grid simulation on million-node designs
Thermal analysis

ThermStack

Geometry-resolved static and transient thermal analysis for 2.5D and 3D chiplet stacks — up to 182× faster than 3D FEM.
Request access

Vertical stacking traps heat between layers, and accelerators now push 700–1200 W — so peak junction temperature decides whether a design ships. ThermStack solves the stack on its real IEEE 3Dblox geometry — every die, bond line, interposer and stepped lid — in a compact proprietary formulation with no meshing step and no convergence tuning, returning the full 3D temperature field at a cost that doesn't grow with how finely the geometry is resolved.

  • Resolved 3D heat maps — full-chip, full-stack temperature fields for 2.5D and 3D assemblies, every die, layer and interposer resolved through-thickness.
  • Transient response — drive the model with arbitrary power waveforms and get the full temperature history at every node.
  • Three engines, one tool — the geometry-resolved numerical solver for sign-off, a bundled FEM-3D reference for ground-truth checks, and ThermStack-AI (GNN) for parametric sweeps — all on identical inputs.
  • Real chiplet stacks — 2.5D interposers, 3D logic stacks, HBM, CPU and RF packages, with anisotropic materials, interface resistance and convective cooling.
Thermal-mechanical stress

WarpStack

Thermal warpage analysis for 2.5D and 3D chiplet packages — a MOR-model for design-space sweeps plus detailed 3D sign-off, from one design description.
Request access

Stacking silicon, interposers and memory bonds materials with very different expansion rates. As the assembly cools from bonding to operating temperature, those mismatches bow the package — and a few microns decides whether solder bumps pull apart into opens or merge into shorts. WarpStack predicts that bow, and where it peaks, in design rather than on the assembly line.

  • A design space in the time of one solve — the MOR-model returns a full warpage map in 51 µs per design point, within 0.04 µm of the 3D reference.
  • 3D for the hard cases — a layer-wise 3D FEM resolves the package through its full thickness on 200+ layer stacks.
  • WarpStack-AI (GNN) — full warpage maps in 19.4 ms at 0.38% error, fast enough for a live optimization loop.
  • Speaks IEEE 3Dblox — validated on a 2nm CoWoS package with 108 chiplets, 8 HBM stacks and 2 GPU dies; CLI with structured JSON in, CSV/JSON out.
Electromigration & reliability

MetalStack

Full-chip, temperature-aware multiphysics: coupled electromigration, thermomigration and IR-drop over real power-grid networks.
Request access

Black's equation and Blech's limit are over-conservative; even physics-based Korhonen solvers usually assume a uniform die temperature. MetalStack closes that gap. It solves the discretized Korhonen stress equation coupled to an MNA IR-drop solver, driven by real spatial thermal maps — and the results show that where the hotspot sits relative to the critical current paths can matter more than the average temperature.

  • Coupled EM / TM / IR-drop — electromigration and thermomigration evolve together with the electrical network, not in isolation.
  • Realistic spatial thermal maps — accepts external chip-level temperature fields, including real measured profiles, in place of a uniform-die assumption.
  • Joule self-heating — per-node, per-segment wire temperature from current density and path resistance, superimposed on the ambient field.
  • Iterative resistance feedback — void-driven resistance changes are written back to the netlist, so every IR-drop solve reflects the grid's current aging state.
  • Monte Carlo lifetime prediction — TTF distributions, not a single number, across sampled material parameters.
  • Flow integration — operates on power grids from open-source OpenROAD and major commercial EDA flows, retaining via resistances for early-failure assessment.
DesignTreesMax nodesInit IR %Final IR %TTF (s)Krylov speedup
armcore_logic20810,9008.8522.211.05×10⁷1.29×
risc_core1865,7506.1929.642.47×10⁷1.21×
JPEG_new1786,3006.566.77>5.0×10⁷1.26×
AES_new973,4506.146.86>5.0×10⁷1.21×
armcore_pad681,7000.290.29>5.0×10⁷1.18×
dual_ram551,4500.090.10>5.0×10⁷1.50×

Power grids extracted from a major commercial EDA design flow, synthesized and placed-and-routed with the SAED32 (32/28 nm) library. Rational Krylov acceleration achieves 0% error on TTF and final-IR metrics vs. the full FDTD reference.

Power integrity

GridStack

Rapid Analysis of Power-grid Transients via Order Reduction — full transient P/G simulation and dynamic IR-drop on million-node grids.
Request access

Dynamic IR-drop is decided by the full time-domain response of a mesh with millions of nodes, thousands of switching sources, and thousands of time steps. A direct solver re-solves that system step after step — trustworthy, far too slow to keep in a design loop. GridStack never re-solves the full mesh: it distills the grid's dominant dynamics into a compact order-10 rational-Krylov model, marches that through time, and projects back onto your probe nodes.

  • Full time-domain waveforms — V(t) at every probe node under arbitrary switching-current profiles; droop, settling, and dynamic IR-drop step by step.
  • Advanced Krylov subspace reduction — a rational subspace places expansion points for the transient window; an order-10 model reproduces the full response.
  • Domain decomposition — partitions the grid into balanced subdomains solved in parallel across multi-core CPUs and GPUs, then stitched at shared boundary nodes.
  • Full-chip visualization — metal-layer structure, rail-aware 2D IR-drop / VSS-bounce maps, and 3D drop surfaces.
  • Built for sweeps — once the reduced model is built, re-running new current scenarios, decap placements, or floorplans is cheap.
Integration · Available now

Ergodex AI

GridStack runs as a callable engine inside Ergodex AI's Electronic Design Lab, where agents run implementation experiments on open EDA flows and propose the next design change. Each experiment calls GridStack for transient IR-drop and power-grid margins, so every candidate is scored against full power-integrity analysis rather than a proxy.

CircuitNodesDirect CPUGridStack CPUSpeedupMax norm. err
ibmpg1t54,2652.27 s0.41 s5.57×5.62e-06
ibmpg2t164,89714.10 s1.19 s11.86×7.39e-08
ibmpg3t1,043,444203.93 s32.64 s6.25×7.94e-07

Reference: direct back-Euler transient solve on the IBM power-grid benchmarks, 1,001 time points, 20 golden probe nodes per circuit, reduction order 10. Average speedup 7.9×.

One suite, the whole integrity picture.

All four engines are in active development and available for evaluation. Tell us about your stack and we'll get you set up.