WarpStack: Warpage Sign-off and Design-Space Exploration for 2.5D/3D Chiplet Packages

Why warpage decides reliability

Stacking silicon, interposers and memory bonds together materials with very different expansion rates. Cycling the package from its assembly temperature to operating temperature turns those mismatches into internal stress, and the whole structure bows and twists. Warpage is a first-order reliability risk in modern 2.5D and 3D integration:

• Opens and shorts. Where the gap between package and board opens too far, a solder joint pulls apart into an open circuit; where it closes too far, neighbouring joints bridge into a short. Whether the centre or the edge bumps are at risk depends on the sign of the bow.
• Structural damage and yield. Excessive bow also cracks dies, delaminates layers, and lowers assembly yield.
• It changes with every decision. Floorplan, stack-up and material selection all change how a package warps, so designers need a warpage answer on every iteration.

The stakes are visible at the leading edge. Industry analysis attributed the delay of NVIDIA's Blackwell to CTE mismatch between the GPU chiplets, LSI bridges, RDL interposer and substrate in TSMC's CoWoS-L package — warpage severe enough to force a redesign of the top metal layers and bump structures [1]. This is the failure mode WarpStack computes, at a speed that lets it run while the stack-up is still a choice.

Three methods, one design description

All three methods run from the same inputs and report results in the same format — warpage heatmaps, cross-sections, a 3D stack view, and peak-to-peak bow in microns — so a user or an agent can move between truth, exploration and speed without changing the design description.

Table 1. The three WarpStack methods, measured on the reference design of Section 4.

The 3D method reports the die-level active surface and the package surface separately. The MOR-model is derived from the 3D formulation itself, so it inherits that model's physics rather than learning it from examples; how it is constructed is Noveety AI's core IP. WarpStack-AI learns a package's warpage behaviour from 3D results and then returns the full map without solving.

Workflow

1. Describe the package. A single structured file lists the layer stack, each layer's material, and the placement of every die or module. WarpStack also reads IEEE 3Dblox [2], so designs come straight from the 2.5D/3D-IC ecosystem without hand re-entry.
2. Apply the thermal load. The package is taken from its stress-free assembly temperature to operating temperature, so expansion mismatches between layers become real bending.
3. Solve or predict the shape. Run the 3D method for sign-off or the MOR-model for sweeps — or skip the solve and let WarpStack-AI predict the map.
4. Read the result. Warpage heatmaps, cross-sections and peak-to-peak bow, in the same format from every method, ready to compare or pass to a script.

Every step is available from a CLI with structured JSON in and CSV/JSON out, for one design or a whole batch.

Reference design: a 2nm CoWoS package

All results in this paper are measured on one 2nm CoWoS-class package, imported directly from its IEEE 3Dblox description: eight HBM stacks of 12-high DRAM beside two GPU dies on a silicon interposer.

Table 2. The reference design as solved at FEM mesh 64.

The 3D reference answer

The detailed 3D method solves the package through its full thickness: 8 memory stacks with 12 DRAM tiers each, two large compute dies and every bond layer. On the baseline design it predicts a broad central dome falling away at the corners, 1332 µm peak-to-peak on the active surface. On this package the active surface and the continuous package surface agree to within 0.1% of peak-to-peak — the bow is global, so the die-level and package-level views coincide.

MOR-model: a design space in the time of one solve

The MOR-model is built once per design and then evaluates any design point in 51 µs. To test it on a point it was not built from, the ABF substrate modulus was stiffened from 24.0 to 28.8 GPa — a change that moves peak-to-peak warpage by +40.9 µm. Both methods were then run on the same mesh and the same load.

Table 3. MOR-model against a from-scratch 3D solve on the stiffened-substrate what-if. Eight further design points drawn from across the material design space were each solved in full 3D and compared: the worst whole-map difference was 0.006%.

6.1 What the speed buys

On a single core the MOR-model evaluates 70.8 million design points per hour, against 89 for the 3D method. Building it costs 17 minutes of 3D solves — about 25 single 3D runs — so it pays for itself within roughly 25 evaluations, and every evaluation after that is effectively free. That is what turns warpage from a sign-off check into something a designer can sweep.

WarpStack-AI: warpage maps in milliseconds

WarpStack-AI is trained per design on warpage fields produced by the 3D method, then predicts the full map directly from the design description. Every held-out point varies both the material set and the thermal load, and the held-out material configurations are kept entirely out of training, so the network is scored on combinations it was never shown.

Table 4. WarpStack-AI accuracy. Per design point it takes 19.4 ms against 41.54 s for the 3D method — 2,146×.

7.1 One-time cost and break-even

Table 5. Cost to train WarpStack-AI for the reference design.

Training labels come from WarpStack's own 3D formulation, generated far more efficiently than a brute-force sweep: 1,792 labelled warpage fields in 32 minutes rather than the day that solving one design point at a time would take. Past 120 design points the network is cheaper than solving directly, and a 1,000-point sweep drops from 11.5 hours to 83 minutes. Figures in this section were measured on an Apple M3, with inference on a single CPU core.

Warpage inside an agentic design loop

WarpStack is built to be called by autonomous design agents. An agent driving floorplan, stack-up and material decisions invokes WarpStack through its CLI and structured data interface, reads back warpage maps and peak-to-peak margins, and uses them to steer the next candidate. The three methods divide the work naturally:

• Screen the whole design space with the MOR-model or WarpStack-AI.
• Optimize inside a live loop with WarpStack-AI at 19.4 ms per evaluation.
• Sign off the critical candidates with the detailed 3D method against warpage limits before tape-out and assembly.

A compare mode runs the methods side by side on the same design, so it is always visible which designs the fast paths can screen and which truly need 3D.

Scope and limitations

• Illustrative material properties. Mechanical properties for the reference design are illustrative values for the material classes involved, not calibrated 2nm, HBM4 or CoWoS process data. Absolute warpage in microns is therefore indicative rather than a prediction about specific hardware. Solver timings, speedups and the agreement between methods do not depend on those values.
• Accuracy is reported against the 3D method, at FEM mesh 64, not against measured shadow-moiré or other physical warpage data.
• Per-design models. The MOR-model and WarpStack-AI are each built for one design; a new stack-up needs a new build (17 min and 83 min respectively on the reference design).
• Loading. Results here use a single thermal step from the stress-free assembly temperature to operating temperature. Process-history effects are outside the scope of this paper.

Conclusion

WarpStack makes warpage a quantity designers can sweep rather than a check they run once. From a single 3Dblox description it offers detailed 3D analysis for sign-off, a MOR-model that reproduces the 3D surface to within 0.036 µm at 798,000× the speed, and a graph-neural predictor that returns full maps in 19.4 ms at 0.38% error. Because the fast methods are built from, and measured against, the same 3D formulation, their answers stay comparable — and every one of them is a callable step for an agentic design flow.

References

1. P. Garrou, “IFTLE 607: Why NVIDIA's Blackwell Is Having Issues with TSMC CoWoS-L Technology,” 3D InCites, Oct. 2024. 3dincites.com
2. IEEE Standards Association, IEEE 3537 — Standard for 3Dblox: Chiplet Connectivity and Physical Properties Description Language. standards.ieee.org/ieee/3537
3. L. Williams, “Silicon Meets Reality: Why Physics Is Now a First-Order Design Constraint for Chips,” Semiconductor Digest. semiconductor-digest.com
4. VSCLAB, UC Riverside — publications underlying the methods in the NoveetyAI engines. sheldonucr.github.io/published_papers